Data Compression
& Decompression Cores
for ASIC & FPGA Chip Designs.
WHY NZip TECHNOLOGY?
Our technology directly results in significant money savings for both you and your customers. How you might ask? By operating with compressed data, there is less data to be processed!
The benefits of this are:
▶ Increased Processing Performance
▶ Greater Storage Capacity
▶ Higher Data Transmission Rates
▶ Reduced Power Consumption
“Today’s exponentially increasing data volumes and the high cost of storage, make compression essential for the Big Data industry. Although research has concentrated on efficient compression, fast decompression is critical for analytics queries that repeatedly read compressed data.”
EXPERIENCE THE NZip DIFFERENCE
Broad Applicability
NZip IP is ideal for reducing the amount of data that is to be processed, stored or transmitted. This makes it useful in a broad range of applications, such as:
Data transport – satellite, optical, wireless, Ethernet, backplane, etc
NAND flash controllers
NOR flash devices, such as SPI and BPI
Network storage systems
DDR storage systems
Data Centers
BigData Analytics
SSDs
SoC applications
Simplicity
We designed the NZip IP for simplicity of integration, implementation, and verification.
It is a single-clock design; therefore, no asynchronous logic or multi-clock logic.
The only required RAM is externally instantiated, which allows for custom RAM wrappers, testability strategies, error correction, and error injection methodologies, etc.
The IP contains no latches, no multi-cycle paths, no asynchronous logic, or any other techniques that are difficult or error-prone for backend implementation processes.
High Performance
At NZip, we offer an array of configurable options to provide secure, hardware-based, compression and decompression performance to suit the available area and power budget. Whether you are looking for IP to compress and decompress your data, or highly efficient IP with exacting standards, we have we have an answer for you. NZip IP is ideal for offloading processors, reducing memory requirements and decreasing the amount of data that is to be processed, stored, or transmitted.
NZip IP provides a variety of compression ratio options, all with high processing bandwidth and low latency.
Superiority
Included in the deliverables are a fully functional testbench and a SystemVerilog model for your verification needs. The testbench and model set us apart from competitors and assure you exceptional IP for a reliable, efficient, and cost-saving design.
The SystemVerilog model can be incorporated into the testbench for your design. The model produces an exact copy of the data that will egress from the IP and flow through your design. The SystemVerilog model allows your testbench to verify the state of the data at all points in your design. This aligns with standard verification methodology practices and procedures.
EXPERIENCE THE NZip DIFFERENCE
Maximizing Profit
Our NZip Intellectual Property (IP) will save you money in lower manufacturing costs, minimized server expense, and decreased engineering time and expenditure. Offering a wide array of configurable options, we have a solution to meet your companies’ needs. Speak to one of our knowledgeable design staff today to find out how we can save you time and money, as well increase company profit and improve chip performance.
Security Standards
Considerations include explicit circuits to stop leakage of data from one operation to another, even under circumstances of malicious attack. This allows the NZip IP to be deployed in secure systems and secure designs.
Low Power
The NZip IP has been designed for power-gating and clock-tree gating, thereby reducing power losses. Our IP informs external logic when to apply aggressive power saving techniques to the IP without compromising the integrity of its operation. This results in the elimination of unnecessary logic switching and leakage current, thereby, reducing both power and heat.
RAMs include explicit read-enables, to avoid unnecessary powering of internal RAM-read circuits.
Extensive clock-enabling of registers is used throughout the design to further reduce power, even while operating at full speed.
Small Chip Area
Design emphasis has been put on routeability, in addition to transistor count. This allows engineers to design a more efficient and cost-effective chip. The resulting expense and time saved translate directly to increased revenue and decreased project time. The NZip IP reduces engineering frustration and increases development performance.
SPECIAL CONSIDERATIONS
ASIC Deployment
ASICs have additional concerns compared to FPGAs such as reset, clocking, power, RAM methodology, scan, testability, security, etc. These differences are not an afterthought but are fundamentally designed into the IP from the outset. Our IP has integrated features suitable for both ASIC and FPGA implementations.
Reliability
All flip-flops are reset with a consistent methodology and all flip-flops and RAMs are considered to be in an unpredictable state after power on. By resetting all flip-flops, it guarantees the NZip IP resets into the same predetermined state every time, thereby eliminating any unpredictable behavior or unreproducible behavior.
Circuits for data integrity, as well as circuits for data security are included within the IP.
Get in Touch
Whether you have a question, an idea, or just want to say hello, feel free to reach out—we’re here to help.